Unit 9: Capstone — CPU Simulator Portfolio & Career Launchpad

Opening Hook — The BCA Student Who Built a CPU

Learning Outcomes — Bloom's Taxonomy Mapped (12 Outcomes)

Concepts — Portfolio Projects, GATE Prep & Career Guidance

This capstone synthesizes all 8 units of Computer Organization into portfolio-ready projects. For each project, you get: a description, complete Python code, and a README template. Build all 8 and you'll have a GitHub portfolio that gets you hired.

🔧 Portfolio Project 1: Truth Table Generator (Unit 1 — Digital Logic)

Python
# truth_table_generator.py — Portfolio Project 1 (Unit 1: Digital Logic)
import itertools

def gate_and(a, b):  return a & b
def gate_or(a, b):   return a | b
def gate_not(a):     return 1 - a
def gate_nand(a, b): return 1 - (a & b)
def gate_nor(a, b):  return 1 - (a | b)
def gate_xor(a, b):  return a ^ b
def gate_xnor(a, b): return 1 - (a ^ b)

GATES = {'AND': gate_and, 'OR': gate_or, 'NOT': gate_not,
         'NAND': gate_nand, 'NOR': gate_nor,
         'XOR': gate_xor, 'XNOR': gate_xnor}

def evaluate_expression(expr, variables, values):
    """Evaluate a Boolean expression with given variable assignments."""
    env = dict(zip(variables, values))
    tokens = expr.upper().split()
    # Simple recursive-descent parser for: NOT A, A AND B, A OR B, etc.
    result = env.get(tokens[0], 0)
    if tokens[0] == 'NOT':
        result = gate_not(env.get(tokens[1], 0))
        tokens = tokens[2:]
    else:
        tokens = tokens[1:]
    i = 0
    while i < len(tokens) - 1:
        op, operand = tokens[i], tokens[i+1]
        val = env.get(operand, 0)
        if op in GATES:
            result = GATES[op](result, val)
        i += 2
    return result

def generate_truth_table(expression, variables):
    """Generate and print full truth table."""
    header = ' | '.join(variables) + ' | OUTPUT'
    print(header)
    print('-' * len(header))
    for combo in itertools.product([0, 1], repeat=len(variables)):
        result = evaluate_expression(expression, variables, combo)
        row = ' | '.join(str(v) for v in combo)
        print(f"{row} |   {result}")

# Example usage
print("=== Truth Table: A AND B OR NOT C ===")
generate_truth_table("A AND B", ['A', 'B'])

README.md
# 🔢 Truth Table Generator
**Portfolio Project 1 — COA Unit 1: Digital Logic**

## Overview
A Python tool that generates complete truth tables for any Boolean expression
using standard logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR).

## Features
- Supports all 7 basic logic gates
- Generates truth tables for any number of variables
- Clean formatted output suitable for documentation

## Usage
```bash
python truth_table_generator.py
```

## Concepts Demonstrated
- Boolean Algebra fundamentals
- Combinational logic gate operations
- Truth table construction

## Author
[Your Name] | BCA Student | COA Portfolio Project

🔧 Portfolio Project 2: 8-bit Shift Register Simulator (Unit 2 — Sequential Circuits)

Python
# shift_register_simulator.py — Portfolio Project 2 (Unit 2: Sequential Circuits)

class ShiftRegister:
    def __init__(self, size=8):
        self.size = size
        self.register = [0] * size
        self.clock = 0

    def display(self):
        bits = ''.join(str(b) for b in self.register)
        print(f"  Clock {self.clock:2d}: [{bits}]  (Decimal: {int(bits, 2)})")

    def shift_left(self, input_bit=0):
        """Shift all bits left; new bit enters from right."""
        self.clock += 1
        output = self.register[0]
        self.register = self.register[1:] + [input_bit]
        return output

    def shift_right(self, input_bit=0):
        """Shift all bits right; new bit enters from left."""
        self.clock += 1
        output = self.register[-1]
        self.register = [input_bit] + self.register[:-1]
        return output

    def parallel_load(self, data):
        """Load 8 bits simultaneously (PIPO)."""
        self.clock += 1
        self.register = [int(b) for b in f"{data:08b}"]

    def serial_in(self, bit_stream):
        """SISO: Feed bits one at a time, shift right."""
        print("  SISO — Serial In, Serial Out:")
        self.display()
        for bit in bit_stream:
            self.shift_right(bit)
            self.display()

# Demo
sr = ShiftRegister(8)
print("=== 8-Bit Shift Register Simulator ===")
print("\n--- Parallel Load: 10110010 ---")
sr.parallel_load(0b10110010)
sr.display()
print("\n--- Shift Left x3 ---")
for _ in range(3):
    sr.shift_left(1)
    sr.display()
print("\n--- Serial In: [1,0,1,1] ---")
sr2 = ShiftRegister(8)
sr2.serial_in([1, 0, 1, 1])

README.md
# 📟 8-Bit Shift Register Simulator
**Portfolio Project 2 — COA Unit 2: Sequential Circuits**

## Overview
Simulates all 4 types of shift registers: SISO, SIPO, PISO, PIPO.
Visualizes bit movement clock-by-clock.

## Features
- Left shift, Right shift operations
- Parallel load (PIPO)
- Serial input with visual output
- Clock cycle tracking

## Concepts Demonstrated
- Sequential circuit behavior
- Flip-flop based storage
- Clock-driven data movement

🔧 Portfolio Project 3: Fetch-Decode-Execute Simulator (Unit 3 — Basic Computer Organization)

Python
# fetch_decode_execute.py — Portfolio Project 3 (Unit 3: Basic Computer Org)

class BasicComputer:
    def __init__(self, memory_size=256):
        self.memory = [0] * memory_size
        self.PC = 0      # Program Counter
        self.MAR = 0     # Memory Address Register
        self.MBR = 0     # Memory Buffer Register
        self.IR = 0      # Instruction Register
        self.AC = 0      # Accumulator
        self.halted = False
        # Opcodes: 0=HLT, 1=LDA, 2=STA, 3=ADD, 4=SUB, 5=JMP
        self.opcodes = {0:'HLT', 1:'LDA', 2:'STA', 3:'ADD', 4:'SUB', 5:'JMP'}

    def load_program(self, program, start=0):
        for i, instr in enumerate(program):
            self.memory[start + i] = instr

    def fetch(self):
        self.MAR = self.PC
        self.MBR = self.memory[self.MAR]
        self.IR = self.MBR
        self.PC += 1
        print(f"  FETCH:  PC={self.PC-1} → MAR={self.MAR} → MBR={self.MBR:#06x} → IR={self.IR:#06x}")

    def decode_execute(self):
        opcode = (self.IR >> 8) & 0xFF
        operand = self.IR & 0xFF
        name = self.opcodes.get(opcode, '???')
        print(f"  DECODE: opcode={name}({opcode}), operand={operand}")
        if opcode == 0:  # HLT
            self.halted = True
        elif opcode == 1:  # LDA addr
            self.AC = self.memory[operand]
        elif opcode == 2:  # STA addr
            self.memory[operand] = self.AC
        elif opcode == 3:  # ADD addr
            self.AC += self.memory[operand]
        elif opcode == 4:  # SUB addr
            self.AC -= self.memory[operand]
        elif opcode == 5:  # JMP addr
            self.PC = operand
        print(f"  EXEC:   AC={self.AC}, PC={self.PC}")

    def run(self):
        cycle = 0
        while not self.halted and cycle < 100:
            print(f"\n--- Cycle {cycle} ---")
            self.fetch()
            self.decode_execute()
            cycle += 1

# Program: Load 5, Add 3, Store result, Halt
# Memory[50]=5, Memory[51]=3
comp = BasicComputer()
comp.memory[50] = 5
comp.memory[51] = 3
program = [0x0132, 0x0333, 0x0234, 0x0000]  # LDA 50, ADD 51, STA 52, HLT
comp.load_program(program)
comp.run()
print(f"\nResult at Memory[52] = {comp.memory[52]}")

README.md
# 🔄 Fetch-Decode-Execute Simulator
**Portfolio Project 3 — COA Unit 3: Basic Computer Organization**

## Overview
Simulates the fundamental instruction cycle of a von Neumann computer.
Visualizes PC, MAR, MBR, IR, and AC register changes at each step.

## Supported Instructions
| Opcode | Mnemonic | Description          |
|--------|----------|----------------------|
| 0      | HLT      | Halt execution       |
| 1      | LDA addr | Load AC from memory  |
| 2      | STA addr | Store AC to memory   |
| 3      | ADD addr | Add to AC            |
| 4      | SUB addr | Subtract from AC     |
| 5      | JMP addr | Jump to address      |

## Concepts Demonstrated
- Von Neumann architecture
- Instruction cycle (fetch → decode → execute)
- Register transfer operations

🔧 Portfolio Project 4: Simple CPU Simulator (Unit 4 — Central Processing Unit)

Python
# cpu_simulator.py — Portfolio Project 4 (Unit 4: CPU Architecture)
# 8 registers (R0-R7), 10-instruction ISA, step-by-step execution

class CPUSimulator:
    def __init__(self):
        self.registers = [0] * 8   # R0-R7
        self.memory = [0] * 256    # 256 bytes data memory
        self.program = []            # Instruction list
        self.PC = 0
        self.halted = False
        self.cycle = 0
        self.ISA = {
            'LOAD': self._load, 'STORE': self._store,
            'ADD':  self._add,  'SUB':   self._sub,
            'MUL':  self._mul,  'AND':   self._and,
            'OR':   self._or,   'NOT':   self._not,
            'JMP':  self._jmp,  'HLT':   self._hlt,
        }

    def _load(self, rd, val, _):
        self.registers[rd] = val

    def _store(self, rs, addr, _):
        self.memory[addr] = self.registers[rs]

    def _add(self, rd, rs1, rs2):
        self.registers[rd] = self.registers[rs1] + self.registers[rs2]

    def _sub(self, rd, rs1, rs2):
        self.registers[rd] = self.registers[rs1] - self.registers[rs2]

    def _mul(self, rd, rs1, rs2):
        self.registers[rd] = self.registers[rs1] * self.registers[rs2]

    def _and(self, rd, rs1, rs2):
        self.registers[rd] = self.registers[rs1] & self.registers[rs2]

    def _or(self, rd, rs1, rs2):
        self.registers[rd] = self.registers[rs1] | self.registers[rs2]

    def _not(self, rd, rs, _):
        self.registers[rd] = ~self.registers[rs] & 0xFF

    def _jmp(self, addr, _, __):
        self.PC = addr - 1  # -1 because PC increments after

    def _hlt(self, *args):
        self.halted = True

    def load_program(self, instructions):
        self.program = instructions

    def dump_registers(self):
        regs = ' '.join(f"R{i}={v}" for i, v in enumerate(self.registers))
        print(f"  Registers: {regs}")

    def execute(self):
        print("=== CPU Simulator — Execution Trace ===")
        while not self.halted and self.PC < len(self.program):
            instr = self.program[self.PC]
            op = instr[0]
            args = instr[1:] + [0] * (3 - len(instr[1:]))
            print(f"\n  Cycle {self.cycle} | PC={self.PC} | {op} {args}")
            self.ISA[op](*args)
            self.dump_registers()
            self.PC += 1
            self.cycle += 1
        print(f"\n=== Halted after {self.cycle} cycles ===")

# Sample 10-instruction program: Compute (5+3)*2 and store
cpu = CPUSimulator()
cpu.load_program([
    ['LOAD', 0, 5],       # R0 = 5
    ['LOAD', 1, 3],       # R1 = 3
    ['ADD',  2, 0, 1],    # R2 = R0 + R1 = 8
    ['LOAD', 3, 2],       # R3 = 2
    ['MUL',  4, 2, 3],    # R4 = R2 * R3 = 16
    ['STORE',4, 100],     # Memory[100] = R4
    ['LOAD', 5, 255],     # R5 = 255
    ['AND',  6, 4, 5],    # R6 = R4 AND R5
    ['NOT',  7, 6],       # R7 = NOT R6
    ['HLT'],               # Halt
])
cpu.execute()

README.md
# 🖥️ Simple CPU Simulator
**Portfolio Project 4 — COA Unit 4: Central Processing Unit**

## Overview
A complete CPU simulator with 8 general-purpose registers, a 10-instruction
ISA, and step-by-step execution trace. The flagship project of this portfolio.

## Instruction Set Architecture (ISA)
| Instruction | Format              | Description              |
|-------------|---------------------|--------------------------|
| LOAD        | LOAD Rd, imm        | Load immediate to Rd     |
| STORE       | STORE Rs, addr      | Store Rs to memory       |
| ADD         | ADD Rd, Rs1, Rs2    | Rd = Rs1 + Rs2           |
| SUB         | SUB Rd, Rs1, Rs2    | Rd = Rs1 - Rs2           |
| MUL         | MUL Rd, Rs1, Rs2    | Rd = Rs1 * Rs2           |
| AND         | AND Rd, Rs1, Rs2    | Rd = Rs1 AND Rs2         |
| OR          | OR  Rd, Rs1, Rs2    | Rd = Rs1 OR Rs2          |
| NOT         | NOT Rd, Rs          | Rd = NOT Rs              |
| JMP         | JMP addr            | Jump to address          |
| HLT         | HLT                 | Halt execution           |

## Concepts Demonstrated
- CPU architecture (registers, ALU, control unit)
- Instruction Set Architecture design
- Program execution and instruction cycle

🔧 Portfolio Project 5: Priority Interrupt Handler (Unit 5 — I/O Organization)

Python
# priority_interrupt_handler.py — Project 5 (Unit 5: I/O Organization)
import heapq

class Interrupt:
    def __init__(self, device, priority, arrival):
        self.device = device
        self.priority = priority  # Lower number = higher priority
        self.arrival = arrival
    def __lt__(self, other):
        return self.priority < other.priority

class InterruptController:
    def __init__(self):
        self.queue = []  # Min-heap (priority queue)
        self.current = None
        self.stack = []   # For nested interrupts
        self.log = []

    def raise_interrupt(self, device, priority, time):
        intr = Interrupt(device, priority, time)
        heapq.heappush(self.queue, intr)
        self.log.append(f"  T={time}: IRQ raised by {device} (priority {priority})")

    def handle_interrupts(self):
        print("=== Priority Interrupt Handler ===")
        while self.queue:
            intr = heapq.heappop(self.queue)
            if self.current and intr.priority < self.current.priority:
                self.stack.append(self.current)
                print(f"  Preempting {self.current.device} for {intr.device}")
            self.current = intr
            print(f"  Servicing: {intr.device} | Priority: {intr.priority} | ISR executing...")
            if self.stack:
                resumed = self.stack.pop()
                print(f"  Resuming: {resumed.device}")
                self.current = resumed
        print("  All interrupts serviced.\n")

# Demo: Multiple devices with different priorities
ic = InterruptController()
ic.raise_interrupt("Keyboard",  3, 1)
ic.raise_interrupt("Disk",      2, 2)
ic.raise_interrupt("Timer",     0, 3)   # Highest priority
ic.raise_interrupt("Network",   1, 4)
ic.raise_interrupt("Printer",   4, 5)
ic.handle_interrupts()

README.md
# ⚡ Priority Interrupt Handler
**Portfolio Project 5 — COA Unit 5: I/O Organization**

## Overview
Simulates priority-based interrupt handling with preemption, nested
interrupts, and ISR dispatch using a min-heap priority queue.

## Concepts Demonstrated
- Priority interrupt system (hardware-level)
- Interrupt service routines (ISR)
- Preemption and nested interrupt handling
- Daisy-chain priority encoding

🔧 Portfolio Project 6: Cache Simulator (Unit 6 — Memory Organization)

Python
# cache_simulator.py — Project 6 (Unit 6: Memory Organization)

class CacheSimulator:
    def __init__(self, cache_size, block_size, assoc, mapping):
        self.cache_size = cache_size
        self.block_size = block_size
        self.assoc = assoc  # 1=direct, cache_size//block_size=fully, else set
        self.mapping = mapping
        self.num_blocks = cache_size // block_size
        self.num_sets = self.num_blocks // assoc
        self.cache = [[None] * assoc for _ in range(self.num_sets)]
        self.lru = [[0] * assoc for _ in range(self.num_sets)]
        self.hits = 0
        self.misses = 0
        self.time = 0

    def access(self, address):
        self.time += 1
        block_num = address // self.block_size
        set_index = block_num % self.num_sets
        tag = block_num // self.num_sets
        # Check for hit
        for i in range(self.assoc):
            if self.cache[set_index][i] == tag:
                self.hits += 1
                self.lru[set_index][i] = self.time
                return "HIT"
        # Miss — find LRU slot to replace
        self.misses += 1
        lru_idx = self.lru[set_index].index(min(self.lru[set_index]))
        self.cache[set_index][lru_idx] = tag
        self.lru[set_index][lru_idx] = self.time
        return "MISS"

    def simulate(self, addresses):
        print(f"=== Cache Simulator ({self.mapping}) ===")
        print(f"  Size: {self.cache_size}B | Block: {self.block_size}B | Sets: {self.num_sets} | Assoc: {self.assoc}-way")
        for addr in addresses:
            result = self.access(addr)
            print(f"  Addr {addr:3d} → Block {addr//self.block_size:2d} → Set {(addr//self.block_size)%self.num_sets} → {result}")
        total = self.hits + self.misses
        print(f"  Hit Ratio: {self.hits}/{total} = {self.hits/total*100:.1f}%")

# Demo: Compare all three mapping types
addrs = [0, 4, 8, 12, 16, 0, 4, 20, 0, 8, 24, 12, 0, 4]
print()
CacheSimulator(16, 4, 1, "Direct-Mapped").simulate(addrs)
print()
CacheSimulator(16, 4, 4, "Fully-Associative").simulate(addrs)
print()
CacheSimulator(16, 4, 2, "2-Way Set-Associative").simulate(addrs)

🔧 Portfolio Project 7: Booth's Multiplication Calculator (Unit 7 — Computer Arithmetic)

Python
# booths_multiplication.py — Project 7 (Unit 7: Computer Arithmetic)

def to_binary(num, bits):
    if num >= 0: return format(num, f'0{bits}b')
    return format((1 << bits) + num, f'0{bits}b')  # 2's complement

def arithmetic_shift_right(A, Q, Qn1, bits):
    """Arithmetic shift right: preserve sign of A."""
    new_Qn1 = Q & 1
    Q = (Q >> 1) | ((A & 1) << (bits - 1))
    sign = A & (1 << (bits - 1))
    A = (A >> 1) | sign
    return A, Q, new_Qn1

def booths_multiply(M, Q_val, bits=5):
    print(f"=== Booth's Multiplication: {M} × {Q_val} ===")
    mask = (1 << bits) - 1
    A = 0
    Q = Q_val & mask if Q_val >= 0 else ((1 << bits) + Q_val) & mask
    M_val = M & mask if M >= 0 else ((1 << bits) + M) & mask
    Qn1 = 0
    print(f"  Init: A={to_binary(A,bits)} Q={to_binary(Q,bits)} Q-1={Qn1}")
    for i in range(bits):
        Q0 = Q & 1
        if Q0 == 1 and Qn1 == 0:
            A = (A - M_val) & mask
            print(f"  Step {i+1}: Q0Qn1=10 → A = A - M")
        elif Q0 == 0 and Qn1 == 1:
            A = (A + M_val) & mask
            print(f"  Step {i+1}: Q0Qn1=01 → A = A + M")
        else:
            print(f"  Step {i+1}: Q0Qn1={Q0}{Qn1} → No operation")
        A, Q, Qn1 = arithmetic_shift_right(A, Q, Qn1, bits)
        print(f"          ASR: A={to_binary(A,bits)} Q={to_binary(Q,bits)} Q-1={Qn1}")
    result_bin = to_binary(A, bits) + to_binary(Q, bits)
    print(f"  Result: {result_bin} = {M * Q_val}")

booths_multiply(-3, 5)
print()
booths_multiply(7, -4)

🔧 Portfolio Project 8: Pipeline Speedup Calculator (Unit 8 — Pipelining)

Python
# pipeline_calculator.py — Project 8 (Unit 8: Pipelining)

class PipelineCalculator:
    def __init__(self, stages, clock_period_ns):
        self.k = stages
        self.tp = clock_period_ns

    def speedup(self, n):
        """Calculate speedup for n instructions."""
        non_pipeline = n * self.k * self.tp
        pipeline = (self.k + n - 1) * self.tp
        s = non_pipeline / pipeline
        return s, non_pipeline, pipeline

    def throughput(self, n):
        """Instructions completed per nanosecond."""
        pipeline_time = (self.k + n - 1) * self.tp
        return n / pipeline_time

    def efficiency(self, n):
        return self.speedup(n)[0] / self.k * 100

    def detect_hazards(self, instructions):
        """Detect data hazards (RAW, WAR, WAW) in instruction list."""
        hazards = []
        for i in range(len(instructions) - 1):
            curr_dest = instructions[i].get('dest')
            next_srcs = instructions[i+1].get('src', [])
            if curr_dest and curr_dest in next_srcs:
                hazards.append(f"  RAW Hazard: I{i+1}→I{i+2} on {curr_dest}")
        return hazards

    def report(self, n):
        s, t_np, t_p = self.speedup(n)
        print(f"=== Pipeline Performance Report ===")
        print(f"  Stages: {self.k} | Clock: {self.tp}ns | Instructions: {n}")
        print(f"  Non-pipeline time: {t_np}ns")
        print(f"  Pipeline time:     {t_p}ns")
        print(f"  Speedup:           {s:.2f}x")
        print(f"  Throughput:        {self.throughput(n):.4f} instr/ns")
        print(f"  Efficiency:        {self.efficiency(n):.1f}%")
        print(f"  Max Speedup (n→∞): {self.k:.1f}x")

# Demo
pipe = PipelineCalculator(stages=5, clock_period_ns=2)
pipe.report(100)

# Hazard Detection
instrs = [
    {'op':'ADD', 'dest':'R1', 'src':['R2','R3']},
    {'op':'SUB', 'dest':'R4', 'src':['R1','R5']},  # RAW on R1!
    {'op':'MUL', 'dest':'R6', 'src':['R4','R7']},  # RAW on R4!
]
print("\n=== Hazard Detection ===")
for h in pipe.detect_hazards(instrs):
    print(h)

📚 GATE Preparation — Top 40 COA Questions (5 per Unit)

The following 40 questions are organized by unit, covering all 8 units of Computer Organization. Each question is GATE-level with full solutions. See Appendix E for the complete Q&A set.

Full 40 questions with detailed solutions available in Appendix E.

🎯 Career Guidance — 4 Hardware Engineering Paths

Career Path 1: VLSI Design Engineer

Career Path 2: Embedded Systems Engineer

Career Path 3: Firmware Engineer

Career Path 4: FPGA Developer

💰 Hardware vs Software Salary Comparison (Indian Market)

📝 LinkedIn Profile Template for Hardware Engineers

LinkedIn Template
HEADLINE:
"VLSI/Embedded Systems Engineer | CPU Architecture | Verilog | ARM | GATE Qualified | Open to Opportunities"

ABOUT:
Computer Organization enthusiast with hands-on experience in CPU design, cache simulation, and pipeline optimization. Built 8 portfolio projects including a complete CPU simulator with 8 registers and a 10-instruction ISA. Proficient in Python, C, Verilog, and embedded C. GATE qualified with strong fundamentals in digital logic, computer arithmetic, and memory systems.

FEATURED PROJECTS:
• CPU Simulator (Python) — 8 registers, fetch-decode-execute, deployed on GitHub
• Cache Simulator — Direct/Associative/Set-Associative with hit-ratio analysis
• Booth's Multiplication Calculator — Step-by-step signed binary multiplication
• Pipeline Speedup Calculator — Hazard detection and performance analysis

SKILLS:
Digital Logic | Computer Architecture | Verilog/VHDL | ARM Assembly
Cache Design | Pipelining | Booth's Algorithm | Python | C/C++
GATE Preparation | Cadence | Synopsys | Xilinx Vivado

🏢 Interview Prep Roadmap

Learn by Doing — Deploy CPU Simulator to GitHub

YAML
# .github/workflows/test.yml
name: Run Tests
on: [push, pull_request]
jobs:
  test:
    runs-on: ubuntu-latest
    steps:
      - uses: actions/checkout@v3
      - uses: actions/setup-python@v4
        with: { python-version: '3.11' }
      - run: python -m pytest tests/ -v

Cross-Unit Synthesis Problems

MCQ Assessment Bank — 30 Cross-Unit GATE-Style Questions

Remember / Identify (Q1–Q5)

Understand / Explain (Q6–Q10)

Apply (Q11–Q15)

Analyze (Q16–Q20)

Evaluate (Q21–Q25)

Create (Q26–Q30)

Short Answer Questions (8 Questions)

Long Answer Questions (3 Questions, 15 marks each)

        C1   C2   C3   C4   C5   C6   C7   C8   C9
I1:     IF   ID   EX   MEM  WB
I2:          IF   ID   EX   MEM  WB
I3:               IF   ID   EX   MEM  WB
I4:                    IF   ID   EX   MEM  WB
I5:                         IF   ID   EX   MEM  WB

Industry Spotlight — Amit Joshi, Freelancer Turned Hardware Startup Founder

Earn With It — Multiple Paths

Chapter Summary

Earning Checkpoint

— APPENDICES —

✅ Computer Organization: COMPLETE! You are GATE-Ready & Industry-Ready.

[QR: Link to EduArtha video tutorial — COA Capstone & CPU Simulator]