Unit 5: Input-Output Organization

Opening Hook — The Fingerprint That Feeds 80 Crore Indians

Learning Outcomes — Bloom's Taxonomy Mapped

Concept Explanation — I/O Organization from Scratch

1. Peripheral Devices

A computer processor by itself is just a number-crunching machine. It becomes useful only when it can communicate with the outside world — keyboards, monitors, printers, scanners, network cards, and sensors. These external devices are called peripheral devices (or simply peripherals).

The fundamental challenge: peripherals operate at vastly different speeds. A keyboard generates ~10 bytes/second, a mouse ~100 bytes/second, but an NVMe SSD can deliver 7 GB/second. The CPU runs at GHz speeds. How do you connect a snail to a bullet train? That's what I/O organization solves.

Speed Hierarchy
  Device             Speed              Analogy
  ─────────────────  ─────────────────  ──────────────────
  Keyboard           ~10 B/s            🚶 Walking
  Mouse              ~100 B/s           🚲 Cycling
  Printer            ~100 KB/s          🚗 Car
  USB 2.0            ~60 MB/s           🚆 Train
  Gigabit Ethernet   ~125 MB/s          ✈️ Airplane
  SATA SSD           ~600 MB/s          🚀 Rocket
  NVMe SSD           ~7 GB/s            ⚡ Lightning
  CPU ↔ RAM          ~50 GB/s           💫 Speed of Light

2. I/O Interface

Peripherals can't talk directly to the CPU — they speak different "languages" (voltage levels, data formats, speeds). An I/O Interface acts as a translator that sits between the CPU/memory bus and the peripheral device.

Analogy: Think of a post office in a small town. The CPU is the District Collector (DC) who writes orders. The I/O Interface is the post office that receives the DC's order, translates it into the right format (Hindi to local language), and delivers it to the right person (device). The post office also handles incoming letters (data from devices) and routes them to the DC.

  ┌──────────┐                                     ┌──────────────┐
  │          │    Address Bus                       │              │
  │          │══════════════════╗                   │   Peripheral │
  │   CPU    │    Data Bus      ║   ┌────────────┐ │    Device    │
  │          │══════════════════╬══▶│  I/O       │ │  (Printer,   │
  │          │    Control Bus   ║   │ Interface  │═══▶ Scanner,   │
  │          │══════════════════╝   │ (Port/     │ │   Disk...)   │
  │          │                      │  Controller│ │              │
  └──────────┘                      └────────────┘ └──────────────┘
       │                                 │
       │         ┌──────────┐            │
       └════════▶│  Memory  │◀═══════════┘
                 │  (RAM)   │
                 └──────────┘

  Functions of I/O Interface:
  ├── Data Format Conversion (serial ↔ parallel)
  ├── Speed Matching (fast CPU ↔ slow device via buffers)
  ├── Device Selection (address decoding)
  ├── Status Monitoring (ready / busy / error flags)
  └── Control Signal Generation (read, write, strobe)

Memory-Mapped I/O vs Isolated I/O

There are two ways the CPU can address I/O devices:

Memory-Mapped I/O
  ┌──────────────────────────────────────┐
  │     Single Address Space             │
  │  ┌─────────────────────────────┐     │
  │  │  0x0000 ─── RAM             │     │
  │  │  ...                        │     │
  │  │  0x7FFF ─── RAM (ends)      │     │
  │  │  0x8000 ─── Keyboard Port   │ ◀── I/O addresses are
  │  │  0x8004 ─── Display Port    │     part of memory map
  │  │  0x8008 ─── Printer Port    │     │
  │  └─────────────────────────────┘     │
  │  CPU uses: MOV, LOAD, STORE          │
  │  Same instructions for I/O & memory  │
  └──────────────────────────────────────┘

Isolated I/O (I/O-Mapped)
  ┌────────────────────┐   ┌────────────────────┐
  │  Memory Space      │   │  I/O Space          │
  │  0x0000 ─── RAM    │   │  Port 0 ─ Keyboard  │
  │  ...               │   │  Port 1 ─ Display   │
  │  0xFFFF ─── RAM    │   │  Port 2 ─ Printer   │
  │                    │   │                     │
  │  SEPARATE spaces   │   │  SEPARATE spaces    │
  └────────────────────┘   └─────────────────────┘
  CPU uses: IN / OUT (special I/O instructions)
  IO/M̄ control line distinguishes the two spaces

3. Data Transfer Modes — How Data Moves Between CPU and Peripherals

There are three fundamental ways data can move between I/O devices and the CPU/memory. Think of them as three levels of postal service:

Programmed I/O (Polling)
  CPU                          Device
   │                             │
   │──── Read Status ──────────▶ │
   │◀─── Status: NOT READY ──── │
   │                             │
   │──── Read Status ──────────▶ │    ← CPU stuck in
   │◀─── Status: NOT READY ──── │      busy-wait loop
   │                             │      (wasting time!)
   │──── Read Status ──────────▶ │
   │◀─── Status: READY ──────── │    ← Finally ready!
   │                             │
   │──── Read Data ────────────▶ │
   │◀─── Data: 0x4D ─────────── │    ← Data transferred
   │                             │
   ▼                             ▼

Interrupt-Driven I/O
  CPU                          Device
   │                             │
   │ ← doing other work...       │ ← preparing data...
   │    (executing programs)     │
   │                             │
   │◀════ INTERRUPT! ═══════════ │  ← Device signals CPU
   │                             │
   │──── Save context ────┐     │
   │     (push registers) │     │
   │                      ▼     │
   │──── Read Data ────────────▶ │
   │◀─── Data: 0x4D ─────────── │  ← Data transferred
   │                             │
   │──── Restore context ──┐    │
   │     (pop registers)   │    │
   │◀──────────────────────┘    │
   │ ← resume original work     │
   ▼                             ▼

4. Direct Memory Access (DMA) — The Star of Unit 5

DMA is the most important topic in this unit. It appears in GATE every 2–3 years, and understanding it deeply will help you crack both exams and interviews.

How DMA Works — Step by Step

                    ┌─────────────────────────────────────────┐
                    │          DMA CONTROLLER                 │
                    │                                         │
  CPU ◀──────────── │  ┌──────────────┐  ┌──────────────┐    │
   │   Bus Request  │  │ Address Reg  │  │  Word Count  │    │
   │   (BR/HRQ)     │  │  (AR)        │  │  Register    │    │
   │                │  │ Starting     │  │  (WC)        │    │
   │ ──────────────▶│  │ address in   │  │  Number of   │    │
   │   Bus Grant    │  │ memory       │  │  words to    │    │
   │   (BG/HLDA)    │  └──────┬───────┘  │  transfer    │    │
   │                │         │          └──────┬───────┘    │
   │                │  ┌──────┴───────┐         │            │
  ═══ System Bus ═══╬══│ Control      │◀────────┘            │
   │                │  │ Logic        │                      │
   │                │  │ (R/W̄, DMA   │  ┌──────────────┐    │
   │                │  │  Request,    │  │  Data Reg    │    │──▶ I/O Device
   │                │  │  DMA Ack)    │──│  (DR)        │    │
   │                │  └──────────────┘  │  Buffer for  │    │
   │                │                    │  data byte   │    │
   │                │                    └──────────────┘    │
  ┌─┐               └─────────────────────────────────────────┘
  │M│
  │E│   DMA Registers:
  │M│   ├── AR  = Starting memory address
  │O│   ├── WC  = Word count (decrements each transfer)
  │R│   ├── DR  = Data register (holds one word in transit)
  │Y│   └── Control = Direction (Read/Write), DMA mode
  └─┘

DMA Transfer Sequence

DMA Handshake
  Step   CPU                    DMA Controller              Device
  ────   ────────────────────   ─────────────────────────   ──────────
   1     CPU initializes DMA:
         → Loads AR (start addr)
         → Loads WC (word count)
         → Sets direction (R/W)
         → Enables DMA

   2     CPU continues its        DMA waits for device       Device
         normal work...           request...                 prepares data

   3                               Device sends DRQ ◀──────── DRQ
                                   (DMA Request)

   4                               DMA sends BR ────────────▶ CPU
                                   (Bus Request / HRQ)

   5     CPU finishes current
         bus cycle, then sends
         BG (Bus Grant / HLDA) ──▶ DMA takes over bus

   6     CPU floats its                                      
         address/data lines        DMA puts address on bus
         (tri-state)               DMA transfers 1 word:
                                   Device ◀──▶ Memory

   7                               WC = WC - 1
                                   AR = AR + 1
                                   If WC ≠ 0: repeat from 3
                                   If WC = 0: send interrupt
                                   to CPU (transfer complete!)

   8     CPU gets interrupt,
         resumes normal bus
         ownership

DMA Transfer Modes

Cycle Stealing — Timing Diagram
  Bus Ownership Timeline:
  
  Time →  T1   T2   T3   T4   T5   T6   T7   T8   T9   T10  T11  T12
         ┌────┬────┬────┬────┬────┬────┬────┬────┬────┬────┬────┬────┐
  Owner: │CPU │CPU │DMA │CPU │CPU │DMA │CPU │CPU │DMA │CPU │CPU │CPU │
         │    │    │ ↑  │    │    │ ↑  │    │    │ ↑  │    │    │    │
         └────┴────┴────┴────┴────┴────┴────┴────┴────┴────┴────┴────┘
                    │              │              │
                   steal          steal          steal
                  1 word         1 word         1 word

  DMA "steals" one bus cycle, transfers one word,
  then gives bus back. CPU barely notices the slowdown.

5. Input-Output Processor (IOP)

While DMA handles simple block transfers, complex I/O operations need a dedicated processor — the I/O Processor (IOP), also called an I/O Channel.

Analogy: DMA is like a delivery boy who can carry packages from A to B. An IOP is like a logistics manager who can plan routes, handle returns, repackage items, manage multiple deliveries simultaneously, and make decisions without calling the CEO (CPU).

  ┌──────────┐         ┌──────────────────┐
  │          │  CMD    │    I/O Processor  │
  │   CPU    │────────▶│    (Channel)      │
  │ (Main    │         │                   │
  │  Proc.)  │         │  ┌─────────────┐  │       ┌──────────┐
  │          │◀────────│  │ Channel Cmd │  │──────▶│ Device 1 │
  │          │  STATUS │  │ Word (CCW)  │  │       └──────────┘
  └──────────┘         │  └─────────────┘  │       ┌──────────┐
       │               │                   │──────▶│ Device 2 │
       │               │  Own registers,   │       └──────────┘
  ┌────▼─────┐         │  can execute      │       ┌──────────┐
  │  Main    │◀═══════▶│  channel programs │──────▶│ Device 3 │
  │  Memory  │         │                   │       └──────────┘
  └──────────┘         └──────────────────┘

Types of I/O Channels

6. Priority Interrupt System

When multiple devices request CPU attention simultaneously, who goes first? The priority interrupt system decides. It's like a hospital emergency room — a heart attack patient gets treated before someone with a headache, even if the headache patient arrived first.

Daisy Chain Priority

Daisy Chain Priority Interrupt
                                    Priority: Highest ──────────▶ Lowest
  ┌──────┐     ┌──────────┐     ┌──────────┐     ┌──────────┐
  │      │ PI  │ Device 0 │ PO  │ Device 1 │ PO  │ Device 2 │
  │      │────▶│ (Highest │────▶│ (Medium  │────▶│ (Lowest  │
  │ CPU  │     │ Priority)│     │ Priority)│     │ Priority)│
  │      │     │          │     │          │     │          │
  │      │◀════╪══════════╪═════╪══════════╪═════╪══════════╪═══ INT Line
  │      │     │          │     │          │     │          │    (common
  └──────┘     └──────────┘     └──────────┘     └──────────┘    wired-OR)

  INT = Interrupt Request (active when ANY device requests)
  PI  = Priority In (from CPU or previous device)
  PO  = Priority Out (to next device)

  Rule: A device can respond to the acknowledge signal
        ONLY if its PI input is active (1).
        If it has an interrupt pending, it blocks PO (sends 0).
        Otherwise, it passes PI through as PO.

  Example: If Device 1 and Device 2 both request simultaneously,
           Device 1 gets serviced first (it blocks PO to Device 2).

Parallel Priority Interrupt (Hardware)

Parallel Priority — Using Priority Encoder
  ┌──────────┐     ┌───────────────────────┐     ┌──────┐
  │ Device 0 │────▶│                       │     │      │
  │ Device 1 │────▶│   Priority Encoder    │────▶│ CPU  │
  │ Device 2 │────▶│   (Combinational      │     │      │
  │ Device 3 │────▶│    Logic Circuit)     │     │ Gets │
  │ Device 4 │────▶│                       │────▶│vector│
  │ Device 5 │────▶│  Outputs: highest     │     │number│
  │ Device 6 │────▶│  priority device ID   │     │      │
  │ Device 7 │────▶│  as binary code       │     │      │
  └──────────┘     └───────────────────────┘     └──────┘

  8 devices → 3-bit output (2³ = 8 combinations)
  ISR = Interrupt Service Routine (fetched from vector table)

  Advantage: Fastest — all devices checked in ONE clock cycle
  Disadvantage: More hardware (encoder, mask register, etc.)

Software Poll

Instead of hardware priority, the CPU checks each device's status register in software, in a fixed order. The first device found with an interrupt pending gets serviced.

Assembly-style Pseudocode
; Software Polling Routine
POLL:   IN    STATUS_DEV0     ; Read Device 0 status
        BNZ   ISR_DEV0        ; If interrupt pending, jump to ISR
        IN    STATUS_DEV1     ; Read Device 1 status
        BNZ   ISR_DEV1
        IN    STATUS_DEV2     ; Read Device 2 status
        BNZ   ISR_DEV2
        IN    STATUS_DEV3
        BNZ   ISR_DEV3
        JMP   POLL            ; No device pending, keep polling

7. Asynchronous Data Transfer — Handshaking

In synchronous transfer, both sender and receiver are controlled by the same clock. But what if they run at different speeds? Asynchronous transfer uses a handshaking protocol — a conversation of control signals that says "I'm sending" / "I received it" / "Send the next one."

Analogy: Think of handing a heavy box to someone. You don't just throw it — you say "Ready?", they say "Ready!", you hand it over, they say "Got it!", then you pick up the next box. That's handshaking.

  Source (Sender)                     Destination (Receiver)
       │                                     │
       │── places data on bus ──────────────▶│
       │                                     │
       │── sends STROBE pulse (↓) ─────────▶│
       │                                     │── reads data from bus
       │                                     │── sends ACK (↑)
       │◀── ACK received ───────────────────│
       │── removes data from bus             │
       │                                     │── removes ACK (↓)
       │                                     │
  
  Timing:
       Data ─────┬═══════════════════┬─────────────
                 │   Valid Data      │
  STROBE ────────┘                   └──────────────
                                          │
  ACK ───────────────────────────────┐    │
                                     └────┘

  Phase  Source                      Destination         Signals
  ─────  ──────────────────────      ──────────────      ─────────
    1    Places data on bus          —                   DATA valid
         Sets DATA_VALID = 1        —                   DV ↑

    2    —                           Reads data          
         —                           Sets DATA_ACK = 1   DA ↑

    3    Sees ACK, removes data     —                   DV ↓
         Sets DATA_VALID = 0        —

    4    —                           Sees DV↓            DA ↓
         —                           Sets DATA_ACK = 0

  Timing Diagram:
  DATA    ──────┬═══════════════════┬──────────
  DATA_VALID ───┘                   └──────────
  DATA_ACK ──────────┐         ┌───────────────
                     └─────────┘
                1    2    3    4    (phases)

8. UART — Universal Asynchronous Receiver-Transmitter

UART is the most common serial communication protocol. Every Arduino project, GPS module, Bluetooth module (HC-05), GSM module (SIM800), and even your computer's serial port uses UART.

Analogy: Think of UART like sending a telegram. You send one letter at a time (serial), with special "start" and "stop" markers so the receiver knows when a message begins and ends. You also include a check digit (parity) so the receiver can detect errors.

  UART Idle State: Line held HIGH (1)

  ┌────┬───┬───┬───┬───┬───┬───┬───┬───┬────────┬──────┐
  │ ST │ D0│ D1│ D2│ D3│ D4│ D5│ D6│ D7│ Parity │ STOP │
  │ 0  │ b │ b │ b │ b │ b │ b │ b │ b │  bit   │  1   │
  └────┴───┴───┴───┴───┴───┴───┴───┴───┴────────┴──────┘
   ↑     ↑                                   ↑       ↑
   │     │                                   │       │
  Start  8 Data Bits                      Parity   Stop
  Bit    (LSB first)                      (Even/   Bit
  (0)                                      Odd)    (1)

  Total frame = 1 + 8 + 1 + 1 = 11 bits per character

  Example: Sending ASCII 'A' (0x41 = 0100 0001) with Even Parity

  ┌───┬───┬───┬───┬───┬───┬───┬───┬───┬───┬───┐
  │ 0 │ 1 │ 0 │ 0 │ 0 │ 0 │ 0 │ 1 │ 0 │ 0 │ 1 │
  │ S │D0 │D1 │D2 │D3 │D4 │D5 │D6 │D7 │ P │ SP│
  └───┴───┴───┴───┴───┴───┴───┴───┴───┴───┴───┘
       LSB ────────────────────▶ MSB
  
  D0–D7 = 1,0,0,0,0,0,1,0 (binary of 0x41, LSB first)
  Parity = 0 (even parity: total 1s in data = 2, already even)
  
  Baud Rate = bits per second
  Common: 9600, 115200
  At 9600 baud: 1 character = 11 bits / 9600 = 1.146 ms

Learn by Doing — 3-Tier Lab Structure

Python
char = input("Enter a character: ")
ascii_val = ord(char)
print(f"ASCII value of '{char}' = {ascii_val} (decimal) = {bin(ascii_val)} (binary)")

Python
# Convert to 8-bit binary (LSB first for UART)
data_bits = format(ascii_val, '08b')[::-1]  # Reverse for LSB first

# Calculate even parity
ones_count = data_bits.count('1')
parity = '0' if ones_count % 2 == 0 else '1'

# Build frame: Start(0) + Data(8) + Parity(1) + Stop(1)
frame = '0' + data_bits + parity + '1'

print(f"\nUART Frame for '{char}':")
print(f"Start | Data (LSB→MSB) | Parity | Stop")
print(f"  {frame[0]}   | {frame[1:9]}         |   {parity}    |  {frame[-1]}")
print(f"Complete frame: {frame} ({len(frame)} bits)")

Python
baud = 9600
bit_time = 1 / baud  # seconds per bit
frame_time = len(frame) * bit_time * 1000  # milliseconds
print(f"\nAt {baud} baud:")
print(f"Time per bit  = {bit_time*1000:.4f} ms")
print(f"Time per frame = {frame_time:.4f} ms")
print(f"Max characters/sec = {baud // len(frame)}")

Practice Problems — Diagrams, Numericals, Industry & GATE

📐 Diagram-Based Problems (D1–D3)

🔢 Numerical Problems (N1–N6)

🏭 Industry Application Problems (I1–I3)

🎯 GATE-Style Problems (G1–G5)

MCQ Assessment Bank — 30 Questions (Bloom's Mapped)

Remember / Identify (Q1–Q6)

Understand / Explain (Q7–Q12)

Apply / Calculate (Q13–Q18)

Analyze / Compare (Q19–Q24)

Evaluate & Create (Q25–Q30)

Short Answer Questions (8 Questions)

Long Answer Questions (3 Questions)

Industry Spotlight — A Day in the Life

Earn With It — IoT & Embedded Projects

⏱️ Time to First Earning: 3–4 weeks (build an IoT project + create a portfolio on GitHub + apply on Internshala for embedded systems internships)

Chapter Summary

Earning Checkpoint

✅ Unit 5 complete. You've mastered I/O Organization!

[QR: Link to EduArtha video tutorial — I/O Organization]