Computer Organization & Architecture
Unit 8: Introduction to Parallel Processing
From pipelining to multiprocessors — master how modern CPUs execute billions of instructions per second through parallelism, pipelining hazards, and architectural innovations.
⏱️ 6 hrs theory + 4 hrs lab | 🎯 GATE ~2 marks | 🖥️ AWS 1 Crore Requests/sec
💼 Jobs this unlocks: CPU Design Engineer (₹12–25 LPA) | HPC Engineer (₹10–20 LPA) | VLSI Engineer (₹8–18 LPA)
Opening Hook — 1 Crore Requests Per Second
🏢 How Amazon AWS Handles 1 Crore Requests Every Second
When you click "Buy Now" on Amazon during the Great Indian Festival sale, your request is just one of 1 crore (10 million) requests processed every single second across AWS's global infrastructure. Behind this staggering scale lies the same principle you'll learn in this chapter — parallel processing and pipelining.
Every modern CPU in AWS's data centres uses a pipelined architecture — splitting instruction execution into stages so multiple instructions overlap like an assembly line. Their servers use multiprocessor systems with hundreds of cores executing tasks simultaneously. The Intel Xeon and AMD EPYC chips powering AWS use superscalar, out-of-order execution — processing 4–6 instructions per clock cycle.
What if YOU understood how this works? What if you could design pipelined processors, calculate speedups, and understand why your ₹50,000 laptop has 8 cores but your program only uses 1? That's exactly what this chapter teaches you.
Learning Outcomes — Bloom's Taxonomy Mapped (12 Outcomes)
| Bloom's Level | Learning Outcome |
|---|---|
| 🔵 Remember | List the 5 stages of a classic instruction pipeline (IF, ID, EX, MEM, WB) and define each stage's function |
| 🔵 Remember | State Flynn's four classifications (SISD, SIMD, MISD, MIMD) with one real-world example for each |
| 🟢 Understand | Explain pipeline hazards (structural, data, control) and how forwarding, stalling, and branch prediction resolve them |
| 🟢 Understand | Describe the difference between shared-memory and distributed-memory multiprocessor organisations |
| 🟡 Apply | Calculate pipeline speedup using S = nk/(k+n−1) and verify with worked numerical examples |
| 🟡 Apply | Apply Amdahl's Law to compute maximum speedup given fraction of parallelisable code and number of processors |
| 🟠 Analyse | Detect RAW, WAR, and WAW data hazards in a given instruction sequence and insert stalls/forwarding paths |
| 🟠 Analyse | Compare superscalar vs VLIW architectures on issue width, hardware complexity, and compiler dependency |
| 🔴 Evaluate | Evaluate the trade-offs between deeper pipelines (more stages) and increased hazard penalties in real processors |
| 🔴 Evaluate | Assess whether adding more processors is cost-effective using Amdahl's Law for a given workload |
| 🟣 Create | Draw a complete space-time diagram for n instructions in a k-stage pipeline with hazard annotations |
| 🟣 Create | Design a parallel processing solution for a given real-world problem (e.g., image processing, web serving) |