Computer Organization & Architecture

Unit 2: Register Transfer & Micro Operations

From flip-flop arrays to ALU internals — master register transfers, micro operations, bus systems, and build a working shift-register simulator.

⏱️ 5 hrs theory + 3 hrs lab | 🎯 GATE ~3 marks | 🖥️ Intel Core i9 Registers

Section A

Opening Hook — The Registers Inside Your Processor

🖥️ Intel Core i9 — 32 General-Purpose Registers Running at 6 GHz

Right now, inside your laptop or desktop, the Intel Core i9 processor has 32 general-purpose registers, each 64 bits wide. Every single instruction your computer executes — opening Chrome, playing a video, compiling code — involves data moving between these registers at speeds exceeding 6 billion cycles per second.

When you type a = b + c in C, the compiler translates it into register-level operations: Load b into R1, Load c into R2, ADD R1+R2→R3, Store R3 to memory. These tiny operations — called micro operations — are the atomic building blocks of everything a CPU does.

Understanding register transfers and micro operations is understanding how a processor actually thinks. This chapter teaches you the exact language (RTL — Register Transfer Language) that hardware designers at Intel, AMD, and Qualcomm use to describe what happens inside a chip — one clock pulse at a time.

🖥️ Intel🖥️ AMD🇮🇳 Qualcomm India🇮🇳 Samsung R&D🇮🇳 ARM India🇮🇳 ISRO VSSC

A single Intel Core i9-14900K contains over 2 billion transistors forming registers, ALUs, and data paths. Every register transfer you'll study in this chapter happens physically — flip-flops toggling, buses carrying bits, multiplexers selecting paths — all within a chip smaller than your thumbnail. GATE CSE has asked 2–3 marks on register transfer and micro operations every year since 2018.

Section B

Learning Outcomes — Bloom's Taxonomy Mapped

Bloom's Level	Learning Outcome
🔵 Remember	Define register, register transfer, and list all RTL notation symbols with their meanings
🔵 Remember	State the four types of micro operations: register transfer, arithmetic, logic, and shift
🔵 Understand	Explain how a common bus system uses multiplexers to connect multiple registers to a shared data path
🔵 Understand	Describe memory read and memory write operations using RTL notation (DR←M[AR], M[AR]←DR)
🟢 Apply	Trace the step-by-step execution of conditional register transfers with timing diagrams
🟢 Apply	Perform selective-set, selective-clear, selective-complement, and insert operations on binary data
🟢 Analyze	Compare logical, circular, and arithmetic shift operations and predict the output for any 8-bit input
🟢 Analyze	Differentiate SISO, SIPO, PISO, and PIPO shift registers by data flow and application
🟠 Evaluate	Determine the correct ALSU function-select code (S₃S₂S₁S₀) for a given micro operation
🟠 Evaluate	Justify why bus-based architecture is preferred over direct register-to-register connections in CPU design
🟠 Create	Write a Python simulator for an 8-bit shift register supporting all shift types
🟠 Create	Design a complete ALSU operation table mapping function-select bits to arithmetic, logic, and shift outputs