Computer Organization & Architecture
Unit 1: Basics of Digital Systems
From logic gates to flip-flops — master combinational and sequential circuits that form the foundation of every computer ever built.
⏱️ 5 hrs theory + 3 hrs lab | 🎯 GATE ~3 marks | 💰 ₹6–12 LPA | 🖥️ ISRO PSLV
💼 Jobs this unlocks: VLSI Design Engineer (₹6–12 LPA) | Embedded Systems Developer (₹5–10 LPA) | GATE/ISRO/DRDO PSU roles
Opening Hook — The Digital Brain Behind ISRO's PSLV
🚀 PSLV-C58: How Digital Circuits Put India in Orbit
On January 1, 2024, ISRO's PSLV-C58 thundered into the sky carrying the XPoSat satellite. Inside the rocket's flight computer, thousands of digital circuits executed flawlessly at 100 MHz — making life-or-death decisions every 10 nanoseconds.
Combinational circuits computed real-time thrust vector calculations for stage separation — pure logic, no memory, instantaneous output. When the first stage burned out at T+113 seconds, a combinational decoder triggered the pyrotechnic bolts that separated the booster. One wrong gate? The rocket tumbles into the Bay of Bengal.
Sequential circuits tracked the rocket's state — "Are we in Stage 1? Stage 2? Coasting? Payload separation?" — using flip-flops that remember the current state and transition only on clock edges. The flight computer's state machine cycled through 47 distinct states from launch to orbit insertion.
What if YOU understood these circuits? What if you could design the logic that decides when a 320-tonne rocket drops its booster? That's exactly what this unit teaches you — the same fundamentals used by ISRO, Intel, and Qualcomm engineers.
Learning Outcomes — Bloom's Taxonomy Mapped (12 Outcomes)
| Bloom's Level | Learning Outcome |
|---|---|
| 🔵 Remember | LO1: List the five functional units of a computer and identify the role of each unit |
| 🔵 Remember | LO2: State the truth tables for all basic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) and standard combinational circuits |
| 🟢 Understand | LO3: Explain the difference between combinational and sequential circuits with real-world analogies |
| 🟢 Understand | LO4: Describe the operation of SR, D, JK, and T flip-flops using characteristic equations and timing diagrams |
| 🟡 Apply | LO5: Design a Half Adder and Full Adder from truth tables and draw their gate-level circuits |
| 🟡 Apply | LO6: Construct a 4-bit Ripple Carry Adder by cascading Full Adders and trace binary addition through it |
| 🟠 Analyze | LO7: Compare SR, D, JK, and T flip-flops on parameters like race condition, toggling, and input constraints |
| 🟠 Analyze | LO8: Analyze the propagation delay issue in Ripple Carry Adders and contrast with Carry Look-Ahead Adders |
| 🔴 Evaluate | LO9: Evaluate which flip-flop type is most suitable for a given application (counter, register, frequency divider) |
| 🔴 Evaluate | LO10: Justify the use of MUX as a universal logic element and assess trade-offs vs discrete gates |
| 🟣 Create | LO11: Design a 3-bit synchronous counter using JK flip-flops with complete state table and circuit diagram |
| 🟣 Create | LO12: Build a Python simulator that generates truth tables for any n-input combinational circuit |